The present invention relates to a method and apparatus for electroless plating and electroplating metal on a substrate comprising a seed layer. The present invention is applicable to plating copper or a copper alloy on a semiconductor substrate, particularly in forming integrated circuits having submicron design features.
The escalating requirement for high density and performance associated with ultra large scale integration (ULSI) semiconductor wiring require responsive changes in interconnection technology, which is considered one of the most demanding aspects of ULSI. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnect pattern, particularly wherein submicron vias, contacts and trenches have high aspect ratios due to miniaturization.
Conventional semiconductor devices comprise a semiconductor substrate, normally of monocrystalline silicon, and a plurality of sequentially formed dielectric layers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines, a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via opening, while a conductive plug filling a contact opening establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor xe2x80x9cchipsxe2x80x9d comprising three and four levels of metallization are becoming more prevalent as device geometries shrink to submicron levels.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Thus, the interconnection pattern limits the speed of the integrated circuit.
In ULSI structures, high circuit speeds, high packing density and low powered dissipation are required. Consequently, feature sizes must be scaled down. The interconnect related time delays become the major limitation in achieving high circuit speeds. Shrinking device size automatically miniaturizes the interconnect feature size which increases interconnect resistance and interconnect current densities. Poor step coverage of metal and submicron high aspect ratio via holes also increases interconnect resistance and electromigration failures. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As integration density increases and feature size decreases in accordance with deep submicron design rules, the rejection rate due to integrated circuit speed delays approaches and even exceeds 20%.
One way to increase the control speed of semiconductor circuitry is to reduce the resistance of a conductive pattern. Conventional metallization patterns are typically formed by depositing a layer of conductive material, notably aluminum (Al) or an alloy thereof, and etching, or by damascene techniques, wherein trenches are formed in dielectric layers and filled with a conductive material. Excess conductive material on the surface of the dielectric layer is then removed, as by chemical-mechanical polishing. Al is conventionally employed because it is relatively inexpensive, exhibits low resistivity and is relatively easy to etch. However, as the size of openings for vias/contacts and trenches is scaled down to the submicron range, step coverage problems have arisen involving the use of Al which has decreased the reliability of interconnections formed between different wiring layers. Such poor step coverage results in high current density and enhanced electromigration. Moreover, low dielectric constant polyamide materials, when employed as dielectric interlayers, create moisture/bias reliability problems when in contact with Al.
One approach to improved interconnection paths in vias comprises the use of completely filled plugs of a metal, such as tungsten (W). Accordingly, many current semiconductor devices utilizing very large scale integration (VLSI) technology employ Al for a wiring metal and W plugs for interconnections at different levels. However, the use of W is attendant with several disadvantages. For example, most W processes are complex and expensive. Moreover, W has a high resistivity. The Joule heating may enhance electromigration of adjacent Al wiring. Furthermore, W plugs are susceptible to void formation and the interface with the wiring layer usually results in high contact resistance.
Another attempted solution comprises the use of chemical vapor deposition (CVD) or physical vapor deposition (PVD) and elevated temperatures for Al deposition. The use of CVD for depositing Al has proven expensive, while PVD Al deposition requires very high process temperatures incompatible with manufacturing integrated circuitry.
Copper has recently received considerable attention as a replacement material for Al in VLSI interconnect metallization. Copper exhibits superior electromigration properties and has a lower resistivity than Al. In addition, copper has improved electrical properties vis-a-vis W, making copper a desirable metal for use as a conductive plug, as well as conductive wiring. For comparable performance characteristics, Al interconnect lines typically exhibit a current density limit of 2xc3x97105 amp/cm2; whereas, a copper line would typically exhibit a current density limit of 5xc3x97106 amp/cm2. Copper electromigration in interconnect lines has a high activation energy, i.e., up to twice as large as that of Al. Consequently, copper lines that are significantly thinner than Al lines can theoretically be employed, thereby reducing cross-talk and capacitance.
It is expected that a copper interconnect material leads to an improvement of one-half times in the maximum clock frequency of a complementary metal-oxide semiconductor (CMOS) chip vis-a-vis the Al-based interconnects for devices with effective channel ends of about 0.25 micrometers. Such favorable electrical characteristics of copper provide an incentive for developing copper films as interconnect layers in ULSI devices as well as top metal layers. However, there are also disadvantages attendant upon the use of copper. For example, copper metallization is very difficult to etch. Moreover, copper readily diffuses through silicon dioxide, a typical interlayer dielectric material employed in the manufacture of semiconductor devices, and adversely affects the devices.
One conventional approach in attempting to form copper plugs and wirings comprises the use of damascene structures employing chemical mechanical polishing, as in Chow et al., U.S. Pat. No. 4,789,648. However, due to copper diffusion through dielectric interlayer materials, such as silicon dioxide, copper interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium tungsten (TiW), tungsten nitride (WN) and silicon nitride (Si3N4) encapsulating copper. The use of such barrier metals to encapsulate copper is not limited to the interface between copper and the dielectric interlayer, but includes interfaces with other metals as well.
Electroless deposition has been suggested as a technique for forming interconnect structures. Electroless copper deposition is attractive due to low processing costs and high quality copper deposits. In addition, equipment for performing electroless deposition is relatively inexpensive vis-a-vis other semiconductor processing equipment for depositing metals. Electroless deposition also offers the advantageous opportunity for batch processing of wafers, thereby further reducing the cost of electroless deposition and increasing production throughput. However, electroless deposition requires a catalytic surface, i.e., seed layer, for the autocatalytic action to occur. It is difficult to obtain reliable and reproducible electroless copper deposition, since the seed layer surface must maintain catalytic activity for effective electroless deposition of copper.
After the copper has been deposited, either by electroless deposition or by electroplating, a relatively thick layer of copper is typically formed over the top surface of the substrate, such as the dielectric layer. Although the recesses, including trenches and via holes, are typically filled with the conductive material, (e.g., copper), the excess material needs to be removed from the top surface of the substrate prior to further processing of the wafer. A commonly used method of removing the excess copper material and planarizing the copper is known as chemical-mechanical polishing (CMP) planarization. In conventional CMP processing, a reactive agent in a slurry reacts with the surface of the layer to be polished, and the abrasive particles mechanically remove the reacted surface layer. The interaction of the polishing pad abrasive particles, and reactive agent with the layer to be polished results in a polishing. Typically, a wafer is held by a carrier head with the top surface of the wafer pressed face down against the outer surface of a polishing pad. A common two-layer polishing pad, with the upper layer composed of IC-1000 the lower layer composed of SUBA-4, is available from Rodell, Inc, located in Newark, Del. (IC-1000 and SUBA-4 are product names of Rodell, Inc.).
Removal of the excess conductive material, such as copper, by CMP requires the use of a CMP polisher, and reduces the throughput as a certain amount of time is required to remove the thickly deposited conductive layer.
There is a need for a deposition process for depositing a conductive material, such as copper, onto a substrate in a manner that does not require a significant amount of polishing and conductive layer removal.
This and other needs are met by embodiments of the present invention which provide a method of depositing a material by electrochemical plating within recesses in a substrate of a semiconductor. In the method, a diffuser is positioned above a top surface of a substrate of a semiconductor wafer so that the diffuser contact surface is in contact with the substrate top surface. The diffuser has apertures through which flows the material to be deposited within the recesses in the substrate. The diffuser is supplied with the material to be deposited. The diffuser is rotated with respect to the top surface of the substrate of the semiconductor wafer while the diffuser is in contact with the substrate top surface and the material to be deposited flows out of the apertures. In this manner, the material to be deposited flows from the apertures into the recesses. In certain preferred embodiments, the fluid supplied to the diffuser is a source of copper or copper alloy, which serves as the material to be deposited.
One of the advantages of the present invention is the avoidance of significant deposits on the top surface of the substrate due to keeping the diffuser in contact with the substrate top surface during the deposition of the material. The rotation of the diffuser, while maintaining contact between the diffuser and the substrate top surface, ensures that the apertures located on the diffuser contact surface will overlap the recesses in the substrate. Hence, only the recesses will fill with the conductive material, such as copper, and the contact prevents significant deposition on the substrate top surface. Hence, CMP planarization may be completely eliminated by the present invention for the purposes of removing excess conductive material on the top surface of the substrate, or at least substantially reduced.
In another aspect of the present invention, a deposition tool is provided having a wafer support with a support surface for supporting a wafer. The diffuser having a substantially planar contact surface and apertures open at the planar contact surface is provided. A material supply arrangement supplies the diffuser with the material which is to be deposited on the wafer through the apertures. A rotational arrangement rotates either the wafer support or the diffuser to provide relative rotation of the diffuser with respect to the wafer support. A vertical positioning arrangement vertically positions the diffuser and the wafer support with respect to one another such that the contact surface of the diffuser is selectively positionable against a wafer supported on the support surface.
One of the advantages of the deposition tool of the present invention is that the pressure against the wafer and the rotational speed of the diffuser are both controllable so as to allow for the control of the amount of conductive material deposited on the top surface of the substrate. The amount of material remaining on the top surface of the substrate is reduced with higher rotation speeds and higher pressures. Hence, the amount of material remaining on the top surface of the substrate is relatively controllable by the operator of a deposition tool.
The earlier stated needs are also met by another aspect of the present invention which provides a method of depositing copper containing conductive material in a recess of a substrate that has a top surface. The copper containing conductive material is supplied in a flowable form on the top surface of the substrate so that at least some of the copper containing conductive material flows into the recess. Simultaneously, the copper containing conductive material that does not flow into the recess is removed from the top surface of the substrate.